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 19-5117; Rev 1; 5/10
16-Bit Microcontrollers with Infrared Module and Optional USB
General Description
The MAXQ612/MAXQ622 are low-power, 16-bit MAXQM microcontrollers designed for low-power applications including universal remote controls, consumer electronics, and white goods. Both devices use a lowpower, high-throughput, 16-bit RISC microcontroller. Serial peripherals include two universal synchronous/ asynchronous receiver-transmitters (USARTs), two SPIK master/slave communications ports, and an inter-integrated circuit (I2C) bus. The devices also incorporate an IR module with carrier frequency generation and flexible port I/O capable of multiplexed keypad control. The MAXQ622 adds a universal serial bus (USB) with integrated physical interface (PHY). The MAXQ612/MAXQ622 include 128KB of flash memory and 6KB of data SRAM. Intellectual property (IP) protection is provided by a secure memory management unit (MMU) that supports multiple application privilege levels and protects code against copying and reverse engineering. Privilege levels enable vendors to provide libraries and applications to execute on the MAXQ612/MAXQ622, while limiting access to only data and code allowed by their privilege level. For the ultimate in low-power battery-operated performance, the devices include an ultra-low-power stop mode (0.3FA typical). In this mode, the minimum amount of circuitry is powered. Wake-up sources include external interrupts, the power-fail interrupt, and a timer interrupt. The microcontroller runs from a wide operating voltage of 1.70V to 3.6V, and can also be powered from the USB.
S 1.70V to 3.6V Operating Voltage S Can Be Powered from Battery (VDD) or USB (VDDB) S 33 Total Instructions for Simplified Programming S Three Independent Data Pointers Accelerate Data
MAXQ612/MAXQ622
Movement with Automatic Increment/Decrement
S Dedicated Pointer for Direct Read from Code Space S 16-Bit Instruction Word, 16-Bit Data Bus S 16 x 16-Bit General-Purpose Working Registers S Secure MMU for Application Partitioning and IP
Protection
S Memory Features
Applications
Remote Controls Battery-Powered Portable Equipment Consumer Electronics Home Appliances White Goods
Features
S High-Performance, Low-Power, 16-Bit RISC Core S DC to 12MHz Operation Across Entire Operating Range
128KB Flash Memory 512-Byte Sectors 20,000 Erase/Write Cycles per Sector 6KB Data SRAM S USB Features (MAXQ622 Only) USB 2.0 Full-Speed Compatible Hardware Receive and Transmit Buffers for High Throughput Integrated Full-Speed Transceiver On-Chip Termination and Pullup Resistors S Additional Peripherals Power-Fail Warning Power-On Reset (POR)/Brownout Reset Automatic IR Carrier Frequency Generation and Modulation Two 16-Bit Programmable Timers/Counters with Prescaler and Capture/Compare Two SPI Communication Ports Two USART Communication Ports I2C Port Programmable Watchdog Timer 8kHz Nanopower Ring Oscillator Wake-Up Timer Up to 56 General-Purpose I/O S Low Power Consumption 0.3A (typ), 3A (max) in Stop Mode TA = +25NC, Power-Fail Monitor Disabled 4.8mA (typ) at 12MHz, 520A (typ) at 1MHz in Active Mode
Ordering Information/Selector Guide
DATA MEMORY (KB) 6 6 6 USB FULL SPEED No No Yes PIN-PACKAGE 44 TQFN-EP* 64 LQFP 64 LQFP
PART MAXQ612J-0000+ MAXQ612G-0000+ MAXQ622G-0000+
TEMP RANGE 0NC to +70NC 0NC to +70NC 0NC to +70NC
OPERATING VOLTAGE (V) 1.7 to 3.6 1.7 to 3.6 1.7 to 3.6
PROGRAM MEMORY (KB) 128 Flash 128 Flash 128 Flash
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Note: Bare die versions for most of these devices are available. Contact the factory for availability at https://support.maxim-ic.com/micro. MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I2C Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C Bus Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 IR Transmit--Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 IR Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Carrier Burst-Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16-Bit Timers/Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Serial Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 USB Controller (MAXQ622 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Loading Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 In-Circuit Debug and JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-Supply Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-Fail Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2
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16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
TABLE OF CONTENTS (continued)
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LIST OF FIGURES
Figure 1. Series Resistors (RS) for Protecting Against High-Voltage Spikes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. I2C Bus Controller Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3. On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 5. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 7. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIST OF TABLES
Table 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4. Power-Fail Warning Level Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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3
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD with Respect to GND .....-0.3V to +3.6V Voltage Range on Any Lead with Respect to GND Except VBUS .............. -0.3V to (VDD + 0.5V) Voltage Range on VBUS with Respect to GND ....-0.3V to +6.0V Continuous Output Current Any Single I/O Pin ...........................................................25mA All I/O Pins Combined.....................................................25mA Voltage Range on DP, DM with Respect to GND...................................-0.3V to (VBUS + 0.3V) Operating Temperature Range ............................. 0NC to +70NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER Supply Voltage 1.8V Internal Regulator Power-Fail Warning Voltage for Supply Power-Fail Reset Voltage POR Voltage RAM Data-Retention Voltage Active Current SYMBOL VDD VREG18 VPFW VRST VPOR VDRV IDD_1 IDD_2 IS1 Stop-Mode Current IS2 Monitors VDD (Notes 2, 3, 4) Monitors VDD (Note 5) Monitors VDD (Note 6) Sysclk = 12MHz Sysclk = 1MHz (Note 6) Power-Fail Off (Note 7) Power-Fail On TA = +25NC TA = +70NC TA = +25NC TA = +70NC [(3 x IS2) + ((PCI 3) x (IS1 + INANO))]/ PCI 100 375 + 8192 tHFXIN (Note 6) (Notes 6, 11) 10 VGND 0.7 x VDD 0.3 x VDD VDD 150 CONDITIONS MIN VRST 1.62 1.75 1.64 1.0 1.0 4.8 0.52 0.3 2.8 24 30 5.5 0.8 3 13 30 40 FA 1.8 1.8 1.67 TYP MAX 3.6 1.98 1.85 1.70 1.42 UNITS V V V V V V mA
Current Consumption During Power Fail
IPFR
(Notes 6, 8, 9)
FA
Current Consumption During POR Stop-Mode Resume Time Power-Fail Monitor Startup Time Power-Fail Warning Detection Time Input Low Voltage for IRTX, IRRX, RESET, and All Port Pins Input High Voltage for IRTX, IRRX, RESET, and All Port Pins 4
IPOR
(Note 10)
nA
tON
Fs
tPFM_ON tPFW VIL VIH
Fs Fs V V
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16-Bit Microcontrollers with Infrared Module and Optional USB
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER Input Hysteresis (Schmitt) Input Low Voltage for HFXIN SYMBOL VIHYS VIL_HFXIN External driven clock and not feedback connected crystal oscillator External driven clock and not feedback connected crystal oscillator VGND CONDITIONS MIN TYP 300 0.3 x VDD MAX UNITS mV V
MAXQ612/MAXQ622
Input High Voltage for HFXIN IRRX Input Filter Pulse-Width Reject IRRX Input Filter Pulse-Width Accept Output Low Voltage for IRTX
VIH_HFXIN
0.7 x VDD
VDD
V
tIRRX_R tIRRX_A VDD = 3.6V, IOL = 25mA (Note 6) VDD = 2.35V, IOL = 10mA (Note 6) VDD = 1.85V, IOL = 4.5mA VDD = 3.6V, IOL = 11mA (Note 6) VOL VDD = 2.35V, IOL = 8mA (Note 6) VDD = 1.85V, IOL = 4.5mA IOH = -2mA (Note 6) Internal pullup disabled VDD = 3V, VOL = VDD/2 (Note 6) VDD = 2V, VOL = VDD/2 VDD = 3.0V, VOL = 0.4V (Note 6) VDD = 2.0V, VOL = 0.4V (Note 6) VDDIOH current is the sum of VDDIO current and IOH of all GPIO, IOH = 10mA (Note 13) -100 16 17 16 17 VDD - 0.4 25 27 28 30 VDDIO 0.5 0.4 0.4 0.4 300
50
ns ns
1.0 1.0 1.0 0.5 0.5 0.5 VDDIO 15 +100 39 41 39 41 VDD V kW V pF nA V V
VOL_IRTX
Output Low Voltage for RESET and All Port Pins (Note 12) Output High Voltage for IRTX and All Port Pins Input/Output Pin Capacitance for All Port Pins Except DP, DM Input Leakage Current Input Pullup Resistor for RESET, IRTX, IRRX, P0 to P6
VOH CIO IL
RPU
GPIO Supply Output High Voltage
VDDIOH
EXTERNAL CRYSTAL/RESONATOR Crystal/Resonator Crystal/Resonator Period Crystal/Resonator Warmup Time Oscillator Feedback Resistor Crystal ESR EXTERNAL CLOCK INPUT External Clock Frequency External Clock Period External Clock Duty Cycle System Clock Frequency fXCLK tXCLK tXCLK_DUTY fCK HFXOUT = GND 45 fHFXIN fXCLK (Note 13) DC 1/fXCLK 55 12 MHz ns % MHz fHFXIN tHFXIN tXTAL_RDY ROSCF From initial oscillation (Note 6) (Note 6) 0.5 1 1/fHFXIN 8192 x tHFXIN 1.0 1.5 60 12 MHz ns ms MW W
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5
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER System Clock Period NANOPOWER RING TA = +25NC Nanopower Ring Frequency Nanopower Ring Duty Cycle Nanopower Ring Current WAKE-UP TIMER Wake-Up Timer Interval FLASH MEMORY System Clock During Flash Programming/Erase Flash Erase Time Flash Programming Time per Word Write/Erase Cycles Data Retention USB USB Supply Voltage VBUS (Note 15) Transmitting on DP and DM at 12Mbps, CL = 50pF on DP and DM to GND, FRCVDD = 0 Transmitting on DP and DM at 12Mbps, CL = 50pF on DP and DM to GND, FRCVDD = 1 DP = high, DM = low, FRCVDD = 0 (Note 6) DP = high, DM = low, FRCVDD = 1 IVBUSSUS VIHD VILD VOLD VOHD VDI VCM RL = 1.5kI from DP to 3.6V RL = 15kI from DP and DM to GND DP to DM Includes VDI range 2.8 0.2 0.8 2.5 2.0 0.8 0.3 4.5 5.0 5.5 13.5 V mA TA = +25NC fFPSYSCLK tME tERASE tPROG Mass erase Page erase (Note 14) 1 20 20 20 20,000 100 40 40 100 MHz ms Fs Cycles Years tWAKEUP 1/fNANO 65,535/ fNANO s fNANO tNANO INANO TA = +25NC, VDD = POR voltage (Note 6) (Note 6) Typical at VDD = 1.64V, TA = +25C (Note 6) 3 1.7 40 40 13 2.4 60 400 20 kHz % nA SYMBOL tCK CONDITIONS MIN TYP 1/fCK MAX UNITS ns
VBUS Supply Current (Note 16)
IVBUS
3.5 6 0.2 500
mA mA mA FA V V V V V V
VBUS Supply Current During Idle (Note 16) VBUS Suspend Supply Current Single-Ended Input High Voltage DP, DM Single-Ended Input Low Voltage DP, DM Output Low Voltage DP, DM Output High Voltage DP, DM Differential Input Sensitivity DP, DM Common-Mode Voltage Range
IVBUSID
6
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16-Bit Microcontrollers with Infrared Module and Optional USB
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER Single-Ended Receiver Threshold Single-Ended Receiver Hysteresis Differential Output Signal Cross-Point Voltage DP, DM Off-State Input Impedance Driver Output Impedance DP Pullup Resistor USB TIMING DP, DM Rise Time (Transmit) DP, DM Fall Time (Transmit) Rise/Fall Time Matching (Transmit) IR Carrier Frequency SPI (Note 6) SPI Master Operating Frequency SPI Slave Operating Frequency SPI I/O Rise/Fall Time SCLK_ Output Pulse-Width High/Low MOSI_ Output Hold Time After SCLK_ Sample Edge MOSI_ Output Valid to Sample Edge MISO_ Input Valid to SCLK_ Sample Edge Rise/Fall Setup MISO_ Input to SCLK_ Sample Edge Rise/Fall Hold SCLK_ Inactive to MOSI_ Inactive SCLK_ Input Pulse-Width High/Low SSEL_ Active to First Shift Edge 1/tMCK 1/tSCK tSPI_RF tMCH, tMCL tMOH tMOV tMIS tMIH tMLH tSCH, tSCL tSSE tSPI_RF CL = 15pF, pullup = 560W 8 tMCK/2 tSPI_RF tMCK/2 tSPI_RF tMCK/2 tSPI_RF 25 0 tMCK/2 tSPI_RF tSCK/2 fCK/2 fCK/4 24 MHz MHz ns ns ns ns ns ns ns ns ns fIR fCK/2 Hz tR tF tR/tF CL = 50pF CL = 50pF CL = 50pF (Note 6) 4 4 90 20 20 110 ns ns % SYMBOL VSE VSEH VCRS RLZ RDRV RPU Steady-state drive Idle Receiving CL = 50pF (Note 6) 1.3 300 28 0.9 1.425 44 1.575 3.090 CONDITIONS MIN 0.8 200 2.0 TYP MAX 2.0 UNITS V mV V kW W kW
MAXQ612/MAXQ622
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7
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
RECOMMENDED OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0NC to +70NC.) (Note 1) PARAMETER MOSI_ Input to SCLK_ Sample Edge Rise/Fall Setup MOSI_ Input from SCLK_ Sample Edge Transition Hold MISO_ Output Valid After SCLK_ Shift Edge Transition SSEL_ Inactive SCLK_ Inactive to SSEL_ Rising MISO_ Output Disabled After SSEL_ Edge Rise SYMBOL tSIS tSIH tSOV tSSH tSD tSLH tCK + tSPI_RF tSPI_RF 2tCK + 2tSPI_RF CONDITIONS MIN tSPI_RF tSPI_RF 50 TYP MAX UNITS ns ns ns ns ns ns
I2C ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V, TA = 0NC to +70NC.) (Note 1, Figure 1) PARAMETER Input Low Voltage Input High Voltage Input Hysteresis (Schmitt) Output Logic-Low (Open Drain or Open Collector) Output Fall Time from VIH_MIN to VIL_MAX with Bus Capacitance from 10pF to 400pF Pulse Width of Spike Filtering That Must Be Suppressed by Input Filter Input Current on I/O I/O Capacitance SYMBOL VIL_I2C VIH_I2C VIHYS_I2C VOL_I2C CONDITIONS (Note 18) (Note 18) VDD > 2V VDD > 2V, 3mA sink current 0 0.4 STANDARD MODE MIN -0.5 0.7 x VDD MAX 0.3 x VDD FAST MODE MIN -0.5 0.7 x VDD 0.05 x VDD 0 0.4 MAX 0.3 x VDD VDD + 0.5V UNITS V V V V
tOF_I2C
(Notes 19, 20)
250
20 + 0.1CB
250
ns
tSP_I2C
0
50
ns
IIN_I2C CIO_I2C
Input voltage from 0.1 x VDD to 0.9 x VDD
-10
+10 10
-10
+10 10
FA pF
8
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16-Bit Microcontrollers with Infrared Module and Optional USB
I2C BUS CONTROLLER TIMING
(Notes 6, 21) (Figure 2) PARAMETER I2C Bus Operating Frequency System Frequency I2C Bit Rate Hold Time After (Repeated) START Clock Low Period Clock High Period Setup Time for Repeated START Hold Time for Data (Notes 22, 23) Setup Time for Data (Note 24) SDA/SCL Fall Time (Note 20) SDA/SCL Rise Time (Note 20) Setup Time for STOP Bus Free Time Between STOP and START Capacitive Load for Each Bus Line Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) SYMBOL fI2C fSYS fI2C tHD:STA tLOW_I2C tHIGH_I2C tSU:STA tHD:DAT tSU:DAT tF_I2C tR_I2C tSU:STO tBUF CB VnL_I2C 0.1 x VDD 4.0 4.7 400 0.1 x VDD 4.0 4.7 4.0 4.7 0 250 300 1000 3.45 STANDARD MODE MIN 0 0.90 fSYS/8 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 400 300 300 0.9 MAX 100 0 3.60 fSYS/8 FAST MODE MIN MAX 400 UNITS kHz MHz Hz Fs Fs Fs Fs Fs ns ns ns Fs Fs pF V
MAXQ612/MAXQ622
VnH_I2C
0.2 x VDD
0.2 x VDD
V
Note 1: Specifications to 0NC are guaranteed by design and are not production tested. Note 2: VPFW can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V Q3%. The values listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal. Note 3: It is not recommended to write to flash when the supply voltage drops below the power-fail warning levels, as there is uncertainty in the duration of continuous power supply. The user application should check the status of the power-fail warning flag before writing to flash to ensure complete write operations. Note 4: The power-fail warning monitor and the power-fail reset monitor are designed to track each other with a minimum delta between the two of 0.11V. Note 5: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is achieved. Note 6: Guaranteed by design and not production tested. Note 7: IS1 is measured with the USB data RAM powered down. Note 8: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles. Note 9: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or VDD. Outputs do not source/ sink any current. The device is executing code from flash memory. Note 10: Current consumption during POR when powering up while VDD is less than the POR release voltage. Note 11: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected. Note 12: The maximum total current, IOH(MAX) and IOL(MAX), for all listed outputs combined should not exceed 25mA to satisfy the maximum specified voltage drop. This does not include the IRTX output. Note 13: External clock frequency must be 12MHz to support USB functionality. Full-speed USB(12Mbps)-required bit-rate accuracy is Q2500ppm or Q0.25%. This is inclusive of all potential error sources: frequency tolerance, temperature, aging, crystal capacitive loading, board layout, etc. Note 14: Programming time does not include overhead associated with utility ROM interface.
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9
16-Bit Microcontrollers with Infrared Module and Optional USB
Note 15: For USB operation, both VDD and VBUS must be connected. Note 16: FRCVDD is the force VDD power-supply bit (PWCN.10). When FRCVDD = 1, VDDB power switching is disabled, and VDD is always used as the core 3V power supply. Note 17: The ESD protection scheme is in production on existing parts. The 1FF capacitor on VBUS is intended to protect that pin from ESD damage (rather than DP or DM) since it is externally exposed. The ESD test uses 150pF charged to 15kV applied to the 1FF capacitor creating a delta V of approximately 2.25V and limiting the voltage on VBUS. Note 18: Devices that use nonstandard supply voltages that do not conform to the intended I2C bus system levels must relate their input levels to the voltage to which the pullup resistors RP are connected. Note 19: The maximum fall time, tF_I2C of 300ns for the SDA and SCL bus lines is longer than the specificed maximum tOF_I2C of 250ns for the output stages. This allows series protection resistors (RS) to be connected between the SDA/SCL pins and the SDA/SCL bus lines as shown in I2C Bus Controller Timing without exceeding the maximum specified fall time. Note 20: CB = Capacitance of one bus line in pF. Note 21: All values referred to VIH_I2C(MIN) and VIL_I2C (MAX). Note 22: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH_I2C(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 23: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW_I2C) of the SCL signal. Note 24: A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU:DAT R 250ns must be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR_I2C(MAX) + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode I2C specification) before the SCL line is released. Note 25: AC electrical specifications are guaranteed by design and are not production tested.
MAXQ612/MAXQ622
VDD
I2C DEVICE MAXQ612 MAXQ622 P0.3 P0.4 SDA SCL RS RS
I2C DEVICE RP RS RS RP
Figure 1. Series Resistors (RS) for Protecting Against High-Voltage Spikes
S SDA tF_I2C tLOW_I2C SCL tHD:STA tHIGH_I2C tR_I2C tSU:DAT
SR
P
S
tBUF tSU:STA
tHD:DAT
tSU:STO
NOTE: TIMING REFERENCED TO VIH_I2C(MIN) AND VIL_I2C(MAX).
Figure 2. I2C Bus Controller Timing Diagram 10 _____________________________________________________________________________________
16-Bit Microcontrollers with Infrared Module and Optional USB
Pin Configurations
P3.7/INT15 P3.6/INT14 TOP VIEW P3.5/INT13 P2.7/TDO P2.6/TMS P1.0/INT0 P2.4/TCK
MAXQ612/MAXQ622
P2.5/TDI
GND
28
N.C.
27
33
32
31
30
29
26
N.C.
25
24
23
P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4 P1.5/INT5 P1.6/INT6 P1.7/INT7 GND IRTX IRRX P0.0/IRTXM
34 35 36 37 38 39 40 41 42 43 44
22 21 20 19 18 17 16 15 14
P3.4/INT12 P3.3/INT11 P3.2/INT10 P3.1/INT9 P3.0/INT8 HFXOUT HFXIN GND REG18 VDD RESET
MAXQ612
+
1 2 3 4 5 6 7 8 9
*EP
13 12
10
P0.2/TX0 P0.3/RX1/SDA
P0.5/TBA0/TBA1
P0.1/RX0
P0.4/TX1/SCL
P0.6/TBB0
P0.7/TBB1
P2.0/MOSI0
P2.1/MISO0
P2.2/SCLK0
TQFN
*EXPOSED PAD.
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P2.3/SSEL0
11
11
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
Pin Configurations (continued)
P5.2/SCLK1 P5.1/MISO1 P5.3/SSEL1 P5.0/MOSI1
P3.7/INT15
P1.1/INT1
P2.6/TMS
P1.0/INT0
P2.7/TDO
P2.4/TCK
P2.5/TDI
TOP VIEW
N.C.
N.C.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P1.2/INT2 49 P1.3/INT3 50 P1.4/INT4 51 P1.5/INT5 52 P1.6/INT6 53 P1.7/INT7 54 P4.0 55 P4.1 56 P4.2 57 P4.3 58 P4.4 59 P4.5 60 P4.6 61 P4.7 62 GND 63 IRTX 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
N.C.
P3.6/INT14
32 P3.5/INT13 31 P3.4/INT12 30 P3.3/INT11 29 P3.2/INT10 28 P3.1/INT9 27 P3.0/INT8 26 HFXOUT 25 HFXIN 24 GND 23 REG18 22 VDD 21 N.C. 20 N.C. 19 N.C. 18 N.C. 17 N.C.
MAXQ612
P0.0/IRTXM
P0.1/RX0
P0.2/TX0
IRRX
P0.3/RX1/SDA
P0.5/TBA0/TBA1
P0.4/TX1/SCL
P0.6/TBB0
P0.7/TBB1
P2.0/MOSI0
P2.1/MISO0
P2.2/SCLK0
P2.3/SSEL0
GND
GND
LQFP
12
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RESET
N.C.
16-Bit Microcontrollers with Infrared Module and Optional USB
Pin Configurations (continued)
P5.2/SCLK1 P5.1/MISO1 P5.3/SSEL1 P5.0/MOSI1 P3.7/INT15 P1.1/INT1 P2.6/TMS P1.0/INT0 P2.7/TDO P2.4/TCK P2.5/TDI
MAXQ612/MAXQ622
TOP VIEW
N.C.
N.C.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P1.2/INT2 49 P1.3/INT3 50 P1.4/INT4 51 P1.5/INT5 52 P1.6/INT6 53 P1.7/INT7 54 P4.0 55 P4.1 56 P4.2 57 P4.3 58 P4.4 59 P4.5 60 P4.6 61 P4.7 62 GND 63 IRTX 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
N.C.
P3.6/INT14
32 P3.5/INT13 31 P3.4/INT12 30 P3.3/INT11 29 P3.2/INT10 28 P3.1/INT9 27 P3.0/INT8 26 HFXOUT 25 HFXIN 24 GND 23 REG18 22 VDD 21 VDDIO 20 VDDB 19 VBUS 18 DM 17 GND
MAXQ622
P0.0/IRTXM
P0.1/RX0
P0.2/TX0
IRRX
P0.3/RX1/SDA
P0.5/TBA0/TBA1
P0.4/TX1/SCL
P0.6/TBB0
P0.7/TBB1
P2.0/MOSI0
P2.1/MISO0
P2.2/SCLK0
P2.3/SSEL0
GND
GND
LQFP
RESET
DP
Pin Description
PIN MAXQ612 TQFN-EP 13 15, 28, 41 MAXQ612 LQFP 22 8, 24, 35, 63 MAXQ622 LQFP 22 8, 17, 24, 35, 63 NAME POWER PINS VDD GND Supply Voltage Ground Regulator Capacitor. This pin must be connected to ground through a 1.0FF external ceramic-chip capacitor. The capacitor must be placed as close to this pin as possible. No external devices other than the capacitor should be connected to this pin. Exposed Pad (TQFN Only). Connect EP to the ground plane. 13 FUNCTION
14
23
23
REG18
--
--
--
EP
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16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
Pin Description (continued)
PIN MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP NAME RESET PINS Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 4mA. This pin is driven low as an output when an internal reset condition occurs. CLOCK PINS 16 17 25 26 25 26 HFXIN HFXOUT High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external, high-frequency clock source when HFXOUT is shorted to ground during POR. USB FUNCTION PINS -- -- 19 VBUS USB VBUS Supply Voltage. Connect VBUS to a positive 5.0V power supply. Bypass VBUS to ground with a 1.0FF ceramic capacitor as close to the VBUS pin as possible. USB D+ Signal. This bidirectional pin carries the positive differential data or single-ended data. Connect this pin to a USB "B" connector. This pin is weakly pulled high internally when the USB is disabled. USB D- Signal. This bidirectional pin carries the negative differential data or single-ended data. Connect this pin to a USB "B" connector. This pin is weakly pulled high internally when the USB is disabled. USB Transceiver Supply Voltage. This is the power output of the internal voltage regulator that is used for the USB transceiver (3.3V) block. This pin is bypassed to ground with a 1.0FF capacitor as close as possible to the package. No external circuitry should be powered from this pin. Switched 3V Power Supply. This is the power output after selection between VBUS and VDD. Must be connected to an external ceramic chip capacitor. The capacitor must be placed as close to this pin as possible. No external devices other than the capacitor should be connected to this pin. IR FUNCTION PINS IR Transmit Output. Active-low IR transmit pin capable of sinking 25mA. This pin defaults to three-state input with the weak pullup disabled during all forms of reset. Software must configure this pin after release from reset to remove the three-state input condition. IR Receive Input FUNCTION
12
15
15
RESET
--
--
16
DP
--
--
18
DM
--
--
20
VDDB
--
--
21
VDDIO
42
64
64
IRTX
43
1
1
IRRX
14
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16-Bit Microcontrollers with Infrared Module and Optional USB
Pin Description (continued)
PIN MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP NAME FUNCTION
MAXQ612/MAXQ622
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. All port pins default to three-state mode after a reset. All alternate functions must be enabled from software. P0.0-P0.7; IRTXM, RX0, TX0, RX1, TX1, SDA, SCL, TBA0, TBA1, TBB0, TBB1 MAXQ612 TQFN-EP 44 1 2 3 4 5 6 7 MAXQ612 LQFP 2 3 4 5 6 7 9 10 MAXQ622 LQFP 2 3 4 5 6 7 9 10 PORT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 SPECIAL FUNCTION IRTXM RX0 TX0 RX1/SDA TX1/SCL TBA0/TBA1 TBB0 TBB1
44, 1-7
2-7, 9, 10
2-7, 9, 10
General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins or as interrupts. All port pins default to three-state mode after a reset. All interrupt functions must be enabled from software. MAXQ612 TQFN-EP 33-40 45, 48-54 45, 48-54 P1.0-P1.7; INT0-INT7 33 34 35 36 37 38 39 40 MAXQ612 LQFP 45 48 49 50 51 52 53 54 MAXQ622 LQFP 45 48 49 50 51 52 53 54 PORT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 SPECIAL FUNCTION INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
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15
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
Pin Description (continued)
PIN MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP NAME FUNCTION General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. P2.0 to P2.3 default to three-state mode after a reset. All alternate functions must be enabled from software. Enabling the pin's special function disables the general-purpose I/O on the pin. The JTAG pins (P2.4 to P2.7) default to their JTAG function with weak pullups enabled after a reset. The JTAG function can be disabled using the TAP bit in the SC register. P2.7 functions as the JTAG test-data output on reset and defaults to an input with a weak pullup. The output function of the test data is only enabled during the TAP's shift_IR or shift_DR states. MAXQ612 TQFN-EP 8 9 10 11 29 30 31 32 MAXQ612 LQFP 11 12 13 14 41 42 43 44 MAXQ622 LQFP 11 12 13 14 41 42 43 44 PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 SPECIAL FUNCTION MOSI0 MISO0 SCLK0 SSEL0 TCK TDI TMS TDO
8-11, 29-32
11-14, 41-44
11-14, 41-44
P2.0-P2.7; MOSI0, MISO0, SCLK0, SSEL0, TCK, TDI, TMS, TDO
General-Purpose, Digital, I/O, Type D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins or as interrupts. All port pins default to three-state mode after a reset. All interrupt functions must be enabled from software. MAXQ612 TQFN 18-25 27-34 27-34 P3.0-P3.7; INT8-INT15 18 19 20 21 22 23 24 25 MAXQ612 LQFP 27 28 29 30 31 32 33 34 MAXQ622 LQFP 27 28 29 30 31 32 33 34 PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 SPECIAL FUNCTION INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15
16
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16-Bit Microcontrollers with Infrared Module and Optional USB
Pin Description (continued)
PIN MAXQ612 TQFN-EP MAXQ612 LQFP MAXQ622 LQFP NAME FUNCTION General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. All port pins default to three-state mode after a reset. MAXQ612 TQFN-EP -- -- 55-62 55-62 P4.0-P4.7 -- -- -- -- -- -- -- MAXQ612 LQFP 55 56 57 58 59 60 61 62 MAXQ622 LQFP 55 56 57 58 59 60 61 62 PORT P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 SPECIAL FUNCTION -- -- -- -- -- -- -- --
MAXQ612/MAXQ622
--
37-40
37-40
P5.0-P5.3; MOSI1, MISO1, SCLK1, SSEL1
General-Purpose, Digital, I/O, Type C Port. These port pins function as bidirectional I/O pins. All port pins default to three-state mode after a reset. All alternate functions must be enabled from software. Enabling the pin's special function disables the general-purpose I/O on the pin. MAXQ612 TQFN-EP -- -- -- -- MAXQ612 LQFP 37 38 39 40 MAXQ622 LQFP 37 38 39 40 PORT P5.0 P5.1 P5.2 P5.3 SPECIAL FUNCTION MOSI1 MISO1 SCLK1 SSEL1
NO CONNECTION PINS 26, 27 16-21, 36, 46, 47 36, 46, 47 N.C. No Connection. Reserved for future use. Leave these pins unconnected.
Detailed Description
The MAXQ612/MAXQ622 provide integrated, low-cost solutions that simplify the design of IR communications equipment such as universal remote controls. Standard features include the highly optimized, single-cycle, MAXQ, 16-bit RISC core; 128KB of flash memory; 6KB data RAM; soft stack; 16 general-purpose registers; and three data pointers. The MAXQ core has the industry's best MIPS/mA rating, allowing developers to achieve the same performance as competing microcontrollers at substantially lower clock rates. Lower active-mode current combined with the even lower MAXQ612/MAXQ622 stop-mode current results in increased battery life. IR application-specific peripherals include flexible timers
for generating IR carrier frequencies and modulation. A high-current, 25mA, IR drive pin and output pins capable of sinking up to 5mA support IR applications. It also includes a USB slave interface compatible with existing host HID device drivers, I2C, dual SPI, dual USARTs, up to 56 general-purpose I/O pins ideal for keypad matrix input, and a power-fail-detection circuit to notify. Operating from DC to 12MHz, almost all instructions execute in a single clock cycle (83.3ns at 12MHz), enabling nearly 12MIPS true-code operation. When active device operation is not required, an ultra-low-power stop mode can be invoked from software, resulting in quiescent current consumption of less than 300nA typical and 3FA maximum. The combination of high-performance instructions and ultra-low
17
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16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
stop-mode current increases battery life over competing microcontrollers. An integrated POR circuit with brownout support resets the device to a known condition following a power-up cycle or brownout condition. Additionally, a powerfail warning flag is set, and a power-fail interrupt can be generated when the system voltage falls below the powerfail warning voltage, VPFW. The power-fail warning feature allows the application to notify the user that the system supply is low and appropriate action should be taken. Memory is accessed through specific data-pointer registers with autoincrement/decrement support.
Memory
The microcontroller incorporates several memory types: * 128KB program flash memory * 6KB SRAM data memory * 6KB utility ROM * Soft stack The optional memory-protection feature separates code memory into three areas: system, user loader, and user application. Code in the system area can be kept confidential. Code in the user areas can be prevented from reading and writing system code. The user loader can also be protected from user application code. Memory protection is implemented using privilege levels for code. Each area has an associated privilege level. RAM/ROM are assigned privilege levels as well. Refer to the MAXQ622 User's Guide for a more thorough explanation of the topic. A 16-bit-wide internal stack provides storage for program return addresses and can also be used for generalpurpose data storage. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An application can also store values in the stack explicitly by using the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (BF0h). The CALL, PUSH, and interrupt-vectoring operations decrement SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then increment SP. The utility ROM is a 6KB block of internal ROM memory that defaults to a starting address of 8000h. The utility
Microprocessor
The MAXQ612/MAXQ622 are based on Maxim's MAXQ20 core, which is a low-power implementation of the new 16-bit MAXQ family of RISC cores. The core supports the Harvard memory architecture with separate internal 16-bit program and data address buses. A fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. The MAXQ core is a pipelined processor with performance approaching 1MIPS per MHz. The 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. The accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (ALU). Program flow is supported by a configurable soft stack. Execution of instructions is triggered by data transfer between functional register modules or between a functional register module and memory. Because data movement involves only source and destination modules, circuit switching activities are limited to active modules only. For power-conscious applications, this approach localizes power dissipation and minimizes switching noise. The modular architecture also provides a maximum of flexibility and reusability that are important for a microprocessor used in embedded applications. The MAXQ instruction set is highly orthogonal. All arithmetical and logical operations can use any register in conjunction with the accumulator. Data movement is supported from any register to any other register.
Memory Protection
Stack Memory
Utility ROM
Table 1. Memory Areas and Associated Maximum Privilege Levels
AREA System User Loader User Application Utility ROM Other (RAM) PAGE ADDRESS 0 to ULDR-1 ULDR to UAPP-1 UAPP to top N/A N/A MAXIMUM PRIVILEGE LEVEL High Medium Low High Low
18
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16-Bit Microcontrollers with Infrared Module and Optional USB
ROM consists of subroutines that can be called from application software. These include the following: * In-system programming (bootstrap loader) using JTAG interface * In-circuit debug routines * Test routines (internal memory tests, memory loader, etc.) * User-callable routines for in-application flash memory programming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of system code, or to one of the special routines mentioned. Routines within the utility ROM are user accessible and can be called as subroutines by the application software. More information on the utility ROM functions is contained in the MAXQ622 User's Guide. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. Three password locks protect three different program memory segments. When the PWL is set to one (poweron reset default) and the contents of the memory at addresses 0010h to 001Fh are any value other than FFh or 00h, the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without password. The PWLS bit uses a password that is at ULDR + 0010 to ULDR + 001F, and the PWLL uses a password at UAPP + 0010 to UAPP + 001F. The password is automatically set to all ones following a mass erase.
Watchdog Timer
The internal watchdog timer greatly increases system reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. The watchdog timer functions as the source of both the watchdog timer timeout and the watchdog timer reset. The timeout period can be programmed in a range of 215 to 224 system clock cycles. An interrupt is generated when the timeout period expires if the interrupt is enabled. All watchdog timer resets follow the programmed interrupt timeouts by 512 system clock cycles. If the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires.
MAXQ612/MAXQ622
IR Carrier Generation and Modulation Timer
The dedicated IR timer/counter module simplifies lowspeed infrared (IR) communication. The IR timer implements two pins (IRTX and IRRX) for supporting IR transmit and receive, respectively. The IRTX pin has no corresponding port pin designation, so the standard PD, PO, and PI port control status bits are not present. However, the IRTX pin output can be manipulated high or low using the PWCN.IRTXOUT and PWCN.IRTXOE bits when the IR timer is not enabled (i.e., IREN = 0).
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WD[1:0] 00 01 10 11 WATCHDOG CLOCK Sysclk/215 Sysclk/218 Sysclk/221 Sysclk/224 WATCHDOG INTERRUPT TIMEOUT 2.7ms 21.9ms 174.7ms 1.4s WATCHDOG RESET AFTER WATCHDOG INTERRUPT (s) 42.7 42.7 42.7 42.7
______________________________________________________________________________________
19
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
The IR timer is composed of a carrier generator and a carrier modulator. The carrier generation module uses the 16-bit IR carrier register (IRCA) to define the high and low time of the carrier through the IR carrier high byte (IRCAH) and IR carrier low byte (IRCAL). The carrier modulator uses the IR data bit (IRDATA) and IR modulator time register (IRMT) to determine whether the carrier or the idle condition is present on IRTX. The IRCAH byte defines the carrier high time in terms of the number of IR input clocks, whereas the IRCAL byte defines the carrier low time. * IR Input Clock (fIRCLK) = fSYS/2IRDIV[1:0] * Carrier Frequency (fCARRIER) = fIRCLK/(IRCAH + IRCAL + 2) * Carrier High Time = IRCAH + 1 * Carrier Low Time = IRCAL + 1 * Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2) During transmission, the IRCA register is latched for each IRV downcount interval, and is sampled along with the IRTXPOL and IRDATA bits at the beginning of each new IRV downcount interval so that duty-cycle variation and frequency shifting is possible from one interval to the next. The starting/idle state and the carrier polarity of the IRTX pin can be configured when the IR timer is enabled. During IR transmission (IRMODE = 1), the carrier generator creates the appropriate carrier waveform, while the carrier modulator performs the modulation. The carrier modulation can be performed as a function of carrier cycles or IRCLK cycles dependent on the setting of the IRCFME bit. When IRCFME = 0, the IRV down counter is clocked by the carrier frequency and thus the modulation is a function of carrier cycles. When IRCFME = 1, the IRV down counter is clocked by IRCLK, allowing carrier modulation timing with IRCLK resolution. The IRTXPOL bit defines the starting/idle state as well as the carrier polarity for the IRTX pin. If IRTXPOL = 1, the IRTX pin is set to a logic-high when the IR timer module is enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low when the IR timer is enabled. A separate register bit, IR data (IRDATA), is used to determine whether the carrier generator output is output to the IRTX pin for the next IRMT carrier cycles. When IRDATA = 1, the carrier waveform (or inversion of this waveform if IRTXPOL = 1) is output on the IRTX pin during the next IRMT cycles. When IRDATA = 0, the idle
20
condition, as defined by IRTXPOL, is output on the IRTX pin during the next IRMT cycles. The IR timer acts as a down counter in transmit mode. An IR transmission starts when the IREN bit is set to 1 when IRMODE = 1; when the IRMODE bit is set to 1 when IREN = 1; or when IREN and IRMODE are both set to 1 in the same instruction. The IRMT and IRCA registers, along with the IRDATA and IRTXPOL bits, are sampled at the beginning of the transmit process and every time the IR timer value reload its value. When the IRV reaches 0000h value, on the next carrier clock, it does the following: 1) Reloads IRV with IRMT. 2) Samples IRCA, IRDATA, and IRTXPOL. 3) Generates IRTX accordingly. 4) Sets IRIF to 1. 5) Generates an interrupt to the CPU if enabled (IRIE = 1).
Carrier Generation Module
IR Transmission
The normal transmit mode modulates the carrier based upon the IRDATA bit. However, the user has the option to input the modulator (envelope) on an external pin if desired. The IRDATA bit is output directly to the IRTXM pin (if IRTXPOL = 0) on each IRV downcount interval boundary just as if it were being used to internally modulate the carrier frequency. If IRTXPOL = 1, the inverse of the IRDATA bit is output to the IRTXM pin on the IRV interval downcount boundaries. When the envelope mode is enabled, it is possible to output either the modulated (IRENV[1:0] = 01b) or unmodulated (INENV[1:0] = 10b) carrier to the IRTX pin. When configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX capture function. The IRRXSEL[1:0] bits define which edge(s) of the IRRX pin should trigger the IR timer capture function. Once started, the IR timer (IRV) starts up counting from 0000h when a qualified capture event as defined by IRRXSEL happens. The IRV register is, by default, counting carrier cycles as defined by the IRCA register. However, the IR carrier frequency detect (IRCFME) allows clocking of the IRV register directly with the IRCLK for finer resolution. When IRCFME = 0, the IRCA defined carrier is counted by IRV. When IRCFME = 1, the IRCLK clocks the IRV register. On the next qualified event, it does the following: 1) Captures the IRRX pin state and transfers its value to IRDATA. If a falling edge occurs, IRDATA = 0. If a rising edge occurs, IRDATA = 1.
IR Transmit--Independent External Carrier and Modulator Outputs
IR Receive
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16-Bit Microcontrollers with Infrared Module and Optional USB
2) Transfers its current IRV value to the IRMT. 3) Resets IRV content to 0000h (if IRXRL = 1). 4) Continues counting again until the next qualified event. If the IR timer value rolls over from 0FFFFh to 0000h before a qualified event happens, the IR timer overflow (IROV) flag is set to 1 and an interrupt is generated, if enabled. The IR module continues to operate in receive mode until it is stopped by switching into transmit mode or clearing IREN = 0. A special mode reduces the CPU processing burden when performing IR learning functions. Typically, when operating in an IR learning capacity, some number of carrier cycles are examined for frequency determination. Once the frequency has been determined, the IR receive function can be reduced to counting the number of carrier pulses in the burst and the duration of the combined mark-space time within the burst. To simplify this process, the receive burst-count mode can be used. When RXBCNT = 0, the standard IR receive capture functionality is in place. When RXBCNT = 1, the IRV capture operation is disabled and the interrupt flag associated with the capture no longer denotes a capture. In the carrier burst-count mode, the IRMT register only counts qualified edges. The IRIF interrupt flag now sets if two IRCA cycles elapse without getting a qualified edge. The IRIF interrupt flag thus denotes absence of the carrier and the beginning of a space in the receive signal. The IRCFME bit is still used to define whether the IRV register is counting system IRCLK clocks or IRCA-defined carrier cycles. The IRXRL bit defines whether the IRV register is reloaded with 0000h on detection of a qualified edge (per the IRXSEL[1:0] bits). * 16-bit timer with capture * 16-bit timer with compare * Input/output enhancements for pulse-width modulation * Set/reset/toggle output state on comparator match * Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
MAXQ612/MAXQ622
General-Purpose I/O
The microcontroller provides port pins for general-purpose I/O that have the following features: * CMOS output drivers * Schmitt trigger inputs * Optional weak pullup to VDD when operating in input mode While the microcontroller is in a reset state, all port pins become three-state with both weak pullups and input buffers disabled, unless otherwise noted. From a software perspective, each port appears as a group of peripheral registers with unique addresses. Special function pins can also be used as general-purpose I/O pins when the special functions are disabled. For a detailed description of the special functions available for each pin, refer to the IC-specific user's guide, e.g., the MAXQ622 User's Guide describes all special functions available on the MAXQ612/MAXQ622.
Carrier Burst-Count Mode
Serial Peripherals
The microcontroller supports two independent USARTs, two SPI master/slave communications ports, and an I2C bus. The USART units are implemented with the following characteristics: * 2-wire interface * Full-duplex operation for asynchronous data transfers * Half-duplex operation for synchronous data transfers * Programmable interrupt for receive and transmit * Independent baud-rate generator
USART
16-Bit Timers/Counters
The microcontroller provides two general-purpose timers/counters that support the following functions: * 16-bit timer/counter * 16-bit up/down autoreload * Counter function of external pulse
Table 3. USART Mode Details
MODE Mode 0 Mode 1 Mode 2 Mode 3 TYPE Synchronous Asynchronous Asynchronous Asynchronous START BITS N/A 1 1 1 DATA BITS 8 8 8+1 8+1 STOP BITS N/A 1 1 1 21
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16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
* Programmable 9th bit parity support * Start/stop bit support The dual-integrated SPI interfaces provide independent serial communication channels that communicate synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum SPI master transfer rate is Sysclk/2. When operating as an SPI slave, the MAXQ612/MAXQ622 can support up to Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit or 16-bit value, MSB first. In addition, the SPI module supports configuration of an active SSEL state through the slave active select. Separate pins and registers are used to differentiate between the two SPI ports. The microcontroller integrates an internal I2C bus masby a USB host as a peripheral, characterized by the following endpoints: * EP0: Bidirectional CONTROL endpoint with a 64-byte data storage. * EP1-OUT: BULK (or INT) OUT endpoint. Doublebuffered 64 bytes data storage. * EP2-IN: BULK (or INT) IN endpoint. Double-buffered 64 bytes data storage. * EP3-IN: BULK (or INT) IN endpoint. Single-buffered 64 bytes data storage. The choice to use EP1, EP2, and EP3 as BULK or INTERRUPT endpoints is strictly a function of the endpoint descriptors that the USB controller returns to the USB host during enumeration. The USB controller communicates to a total of 384 bytes of endpoint data memory (2 x 64 bytes for each data moving endpoint EP1 and EP2), 64 bytes for the CONTROL endpoint, and 64 bytes for endpoint EP3. Double-buffering EP1 and EP2 improves throughput by allowing the CPU to read or load the next packet while the USB controller is moving the current packet over USB. EP3-IN is intended to serve as a large interrupt endpoint for various USB class specifications such as the Still Image Capture Device. It can also be used as a second BULK IN endpoint.
Serial Peripheral Interface (SPI)
I2C Bus
ter/slave for communication with a wide variety of other I2C-enabled peripherals. The I2C bus is a 2-wire, bidirectional bus using two bus lines--the serial data line (SDA) and the serial clock line (SCL)--and a ground line. Both the SDA and SDL lines must be driven as opencollector/drain outputs. External resistors are required as shown in Figure 1 to pull the lines to a logic-high state. The device supports both the master and slave protocols. In the master mode, the device has ownership of the I2C bus, drives the clock, and generates the START and STOP signals. This allows it to send data to a slave or receive data from a slave as required. In slave mode, the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I2C master device.
On-Chip Oscillator
An external quartz crystal or a ceramic resonator can be connected between HFXIN and HFXOUT, as illustrated in Figure 3. To operate the core from an external clock, connect the clock source to the HFXIN pin and connect the HFXOUT
VDD HFXIN CLOCK CIRCUIT STOP RF HFXOUT C1 C2 RF = 1MI Q50% C1 = C2 = 12pF
USB Controller (MAXQ622 Only)
The integrated USB controller is compliant with the USB 2.0 specification, providing full-speed operation with the newest generation of USB peripherals. The USB controller functions as a full-speed USB peripheral device. Integrating the USB physical interface (PHY) allows direct connection to the USB cable, reducing board space and overall system cost. A system interrupt can be enabled to signal that the USB needs to be serviced. The CPU communicates to the USB controller module through the SFR interface. The microcontroller is seen
Figure 3. On-Chip Oscillator 22 _____________________________________________________________________________________
16-Bit Microcontrollers with Infrared Module and Optional USB
pin to GND. The clock source should be driven through a CMOS driver. If the clock driver is a TTL gate, its output must be connected to VDD through a pullup resistor to ensure a satisfactory logic level for active clock pulses. To minimize system noise on the clock circuitry, the external clock source must meet the maximum rise and fall times and the minimum high and low times specified for the clock source. The external noise can affect the clock generation circuit if these parameters do not meet the specification. Noise at HFXIN and HFXOUT can adversely affect onchip clock timing. It is good design practice to place the crystal and capacitors as near the oscillator circuitry as possible with a direct short trace. The typical values of external capacitors vary with the type of crystal to be used.
In-Application Flash Programming
From user-application code, flash memory can be programmed using the ROM utility functions from either C or assembly language. The function declarations below show examples of some of the ROM utility functions provided for in-application flash memory programming: /* Write one 16-bit word to code address `dest'. * Dest must be aligned to 16 bits. * Returns 0 = failure, 1 = OK. */
MAXQ612/MAXQ622
int flash_write (uint16_t dest, uint16_t data); To erase, the following function would be used: /* Erase the given Flash page */
ROM Loader
The ROM loader loads program memory and configures loader-specific configuration features. To increase the security of the system, the loader denies access to the system, user loader, or user-application memories unless an area-specific password is provided.
* addr: Flash offset (anywhere within page) int flash_erasepage(uint16_t addr);
The in-application flash memory programming must call ROM utility functions to erase and program any of the flash memory. Memory protection is enforced by the ROM utility functions.
Loading Flash Memory
An internal bootstrap loader allows reloading over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. The interface hardware can be a JTAG connection to another microcontroller, or a connection to a PC serial port using a USB-to-JTAG converter such as the MAXQUSBJTAGKIT#, available from Maxim. If in-system programmability is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and loading the test access port (TAP) with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to one during reset through the JTAG interface executes the bootstrap-loader mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. In addition, the ROM loader also enforces the memoryprotection policies. Passwords that are 16 words are required to access the ROM loader interface.
In-Circuit Debug and JTAG Interface
Embedded debug hardware and software are developed and integrated to provide full in-circuit debugging capability in a user-application environment. These hardware and software features include the following: * Debug engine * Set of registers providing the ability to set breakpoints on register, code, or data using debug service routines stored in ROM Collectively, these hardware and software features support two modes of in-circuit debug functionality: * Background mode: CPU is executing the normal user program Allows the host to configure and set up the in-circuit debugger * Debug mode: Debugger takes over the control of the CPU Read/write accesses to internal registers and memory Single-step of the CPU for trace operation The interface to the debug engine is the TAP controller. The interface allows for communication with a bus
23
______________________________________________________________________________________
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
then (VDDIO = VDDB) else (VDDIO = VDD)
DEBUG SERVICE ROUTINES (UTILITY ROM)
MAXQ612 MAXQ622
CPU DEBUG ENGINE TMS TCK TDI TDO TAP CONTROLLER CONTROL BREAKPOINT ADDRESS DATA
This means that if there is a power-fail event on VDD and the device is not powered from VBUS, it causes a powerfail interrupt (PFI) if enabled. If the device is powered by VBUS and there is a supply on VDD, then no power-fail event is triggered. If the device is powered by VBUS and there is no supply on VDD and VBUS fails, the chip attempts to switch to VDD, detects a power-fail event, and a PFI occurs. Some specific examples are given below: * Case 1: The device is powered from VDD and the batteries are removed. Power decays until the power-fail-reset trip point is hit, then the part goes into low-power mode. * Case 2: The device is set to be powered from VDD only, it is connected to USB, and the batteries are removed. Response is identical to Case 1. * Case 3: The device is set to be powered from either VDD or VBUS, it is connected to USB, and the batteries are removed. Because the part is already powered from VBUS, nothing changes. If the USB port is subsequently disconnected, power switches over to VDD, the supply decays to the power-fail-reset trip point, and the part goes into low-power mode. As long as there is sufficient charge on the VDD bypass capacitor, it supports the part in power-fail. The holdup time is similar to the MAXQ610 since the USB port is powered only by VBUS. Note that if the part is powered from VBUS and no battery has been present for a long time (VDD = 0), then upon USB port disconnection, the power collapses to ground in less than a second. The lowest power mode of operation is stop mode. In this mode, CPU state and memories are preserved, but the CPU is not actively running. Wake-up sources include external I/O interrupts, the power-fail warning interrupt, wake-up timer, or a power-fail reset. Any time the microcontroller is in a state where code does not need to be executed, the user software can put the microcontroller into stop mode. The nanopower ring oscillator is an internal ultra-low-power (400nA) 8kHz ring oscillator that can be used to drive a wake-up timer that exits stop mode. The wake-up timer is programmable by software in steps of 125Fs up to approximately 8s. The power-fail monitor is always on during normal operation. However, it can be selectively disabled during stop
Figure 4. In-Circuit Debugger
master that can either be automatic test equipment or a component that interfaces to a higher level test bus as part of a complete system. The communication operates across a 4-wire serial interface from a dedicated TAP that is compatible with the JTAG IEEE Standard 1149. The TAP provides an independent serial channel to communicate synchronously with the host system. To prevent unauthorized access of the protected memory regions through the JTAG interface, the debug engine prevents modification of the privilege registers and disallows all access to system memory, unless memory protection is disabled. In addition, all services (such as register display or modification) are denied when code is executing inside the system area.
Operating Modes
For maximum flexibility the microcontroller can be powered by either the USB (VBUS) or VDD. When a USB connection is made to a valid VBUS power source, an internal voltage regulator generates a 3.3V supply voltage. When the internal voltage is at an adequate level, it automatically powers itself from the USB supply. This is especially beneficial in systems where the VDD supply is from a battery. In either case, the chip is fully functional when operating from either the battery or the VBUS. The power monitor is attached to the switched supply, VDDIO. This supply is equivalent to the higher of VDDB or VDD. This can be expressed as follows: If (VDDB > 3.0V or VDDB > VDD)
24
Stop Mode
Power-Supply Selection
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16-Bit Microcontrollers with Infrared Module and Optional USB
Table 4. Power-Fail Warning Level Selection
PWCN.PFWARNCN[1:0] 00 01 10 11 PFW THRESHOLD (V) 1.8 1.9 2.55 2.75
mode to minimize power consumption. This feature is enabled using the power-fail monitor disable (PFD) bit in the PWCN register. The reset default state for the PFD bit is 1, which disables the power-fail monitor function during stop mode. If power-fail monitoring is disabled (PFD = 1) during stop mode, the circuitry responsible for generating a power-fail warning or reset is shut down and neither condition is detected. Thus, the VDD < VRST condition does not invoke a reset state. However, in the event that VDD falls below the POR level, a POR is generated. The power-fail monitor is enabled prior to stop mode exit and before code execution begins. If a powerfail warning condition (VDD < VPFW) is then detected, the power-fail interrupt flag is set on stop mode exit. If a power-fail reset condition is detected (VDD < VRST), the CPU goes into reset.
The power-fail monitor can assert an interrupt if the voltage falls below a configurable threshold between the operating voltage and the reset voltage. This, if enabled, can allow the firmware to perform housekeeping tasks if the voltage level decays below the warning threshold. The power-fail threshold value should only be changed when the power-fail warning interrupt is disabled (CKCN. PFIE = 0) to prevent unintended triggering of the powerfail warning condition. The power-fail warning threshold is reset to 1.8V by a POR and is not affected by other resets. See Table 4. Figures 5, 6, and 7 show the power-fail detection and response during normal and stop-mode operation.
Power-Fail Warning
MAXQ612/MAXQ622
Power-Fail Detection
If a reset is caused by a power-fail, the power-fail monitor can be set to one of the following intervals: * Always on--continuous monitoring * 211 nanopower ring oscillator clocks (~256ms) * 212 nanopower ring oscillator clocks (~512ms) * 213 nanopower ring oscillator clocks (~1.024s) In the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two
VDD
t < tPFW C
t tPFW
t tPFW
t tPFW
VPFW VRST E F B D
G H
VPOR A
I
INTERNAL RESET (ACTIVE HIGH)
Figure 5. Power-Fail Detection During Normal Operation
______________________________________________________________________________________
25
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
Table 5. Power-Fail Detection States During Normal Operation
STATE A B POWER-FAIL On On INTERNAL REGULATOR Off On CRYSTAL OSCILLATOR Off On SRAM RETENTION -- -- VDD < VPOR. VPOR < VDD < VRST. Crystal warmup time, tXTAL_RDY. CPU held in reset. VDD > VRST. CPU normal operation. Power drop too short. Power-fail not detected. VRST < VDD < VPFW. PFI is set when VRST < VDD < VPFW and maintains this state for at least tPFW, at which time a power-fail interrupt is generated (if enabled). CPU continues normal operation. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodically. VDD > VRST. Crystal warmup time, tXTAL_RDY. CPU resumes normal operation from 8000h. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodically. VDD < VPOR. Device held in reset. No operation allowed. COMMENTS
C D
On On
On On
On On
-- --
E
On
On
On
--
F
On (Periodically)
Off
Off
Yes
G
On
On
On
--
H
On (Periodically)
Off
Off
Yes
I
Off
Off
Off
--
nanopower ring-oscillator cycles. If VDD > VRST during detection, VDD is monitored for an additional nanopower ring-oscillator period. If VDD remains above VRST for the third nanopower ring period, the CPU exits the reset state and resumes normal operation from utility ROM at 8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the RESET pin being driven low externally or the watchdog timer, the power-fail, internal regulator, and crystal remain on during the CPU reset. In these cases, the CPU exits the reset state in less than 20 crystal cycles after the reset source is removed.
26
_____________________________________________________________________________________
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
VDD A t < tPFW t tPFW t tPFW
VPFW VRST B C
D
E VPOR F
STOP
INTERNAL RESET (ACTIVE HIGH)
Figure 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. Power drop too short. Power-fail not detected. VRST < VDD < VPFW. Power-fail warning detected. Turn on regulator and crystal. Crystal warmup time, tXTAL_RDY. Exit stop mode. Application enters stop mode. VDD > VRST. CPU in stop mode. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodically. VDD < VPOR. Device held in reset. No operation allowed.
A
On
B
On
Off
Off
Yes
C
On
On
On
Yes
D
On
Off
Off
Yes
E
On (Periodically)
Off
Off
Yes
F
Off
Off
Off
--
______________________________________________________________________________________
27
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
VDD A D VPFW VRST B C
E VPOR F
STOP
INTERNAL RESET (ACTIVE HIGH)
INTERRUPT
Figure 7. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. VDD < VPFW. Power-fail not detected because power-fail monitor is disabled. VRST < VDD < VPFW. An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a power-fail warning, and sets the power-fail interrupt flag. Turn on regulator and crystal. Crystal warmup time, tXTAL_RDY. On stop mode exit, CPU vectors to the higher priority of power-fail and the interrupt that causes stop mode exit.
A
Off
B
Off
Off
Off
Yes
C
On
On
On
Yes
28
_____________________________________________________________________________________
16-Bit Microcontrollers with Infrared Module and Optional USB
Table 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled (continued)
STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. VPOR < VDD < VRST. An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a power-fail, and puts CPU in reset. Power-fail monitor is turned on periodically. VDD < VPOR. Device held in reset. No operation allowed.
MAXQ612/MAXQ622
D
Off
E
On (Periodically)
Off
Off
Yes
F
Off
Off
Off
--
Applications Information
The low-power, high-performance RISC architecture of this device makes it an excellent fit for many portable or battery-powered applications. It is ideally suited for applications such as universal remote controls that require the cost-effective integration of IR transmit/ receive capability. Careful PCB layout significantly minimizes system-level digital noise that could interact with the microcontroller or peripheral components. The use of multilayer boards is essential to allow the use of dedicated power planes. The area under any digital components should be a continuous ground plane if possible. Keep bypass capacitor leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible. CMOS design guidelines for any semiconductor require that no pin be taken above VDD or below GND. Violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (unintentional modification of memory contents). Voltage spikes above or below the device's absolute maximum ratings can potentially cause a devastating IC latchup. Microcontrollers commonly experience negative voltage spikes through either their power pins or general-
purpose I/O pins. Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. Devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System designers must protect components against these transients that can corrupt system memory.
Grounds and Bypassing
Additional Documentation
Designers must have the following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers. * This MAXQ612/MAXQ622 data sheet, which contains electrical/timing specifications and pin descriptions. * The MAXQ612 /MAXQ622 revision-specific errata sheet (www.maxim-ic.com/errata). * The MAXQ622 User's Guide, which contains detailed information on features and operation, including programming.
______________________________________________________________________________________
29
16-Bit Microcontrollers with Infrared Module and Optional USB MAXQ612/MAXQ622
Block Diagram
MAXQ612/MAXQ622 REGULATOR VOLTAGE MONITOR GPIO USB SIE* TXCVR *MAXQ622 ONLY. 16-BIT MAXQ RISC CPU 6KB ROM CLOCK WATCHDOG 2x 16-BIT TIMER SECURE MMU 128KB FLASH 6KB SRAM 8kHz NANO RING IR DRIVER IR TIMER 2x SPI 2x USART I2C
Development and Technical Support
Maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: * Compilers * In-circuit emulators * Integrated Development Environments (IDEs) * JTAG-to-serial converters for programming and debugging A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. For technical support, go to https://support.maxim-ic. com/micro.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 64 LQFP 44 TQFN-EP PACKAGE CODE C64+5 T4477+2 DOCUMENT NO. 21-0083 21-0144
30
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16-Bit Microcontrollers with Infrared Module and Optional USB
Revision History
REVISION NUMBER 0 1 REVISION DATE 2/10 5/10 Initial release Changed the VDDIOH spec for IOH from IOH = 20mA to IOH = 10mA in the Recommended Operating Conditions table DESCRIPTION PAGES CHANGED -- 5
MAXQ612/MAXQ622
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
31
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.


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